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Wafer backgrinding

Known as: Backlap, Wafer thinning 
Wafer backgrinding is a semiconductor device fabrication step during which wafer thickness is reduced to allow for stacking and high density… 
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Related topics

Related topics

7 relations
Back end of lineBack-illuminated sensorEtching (microfabrication)Microelectromechanical systems

Papers overview

Semantic Scholar uses AI to extract papers important to this topic.
2013
2013
Non-invasive pre-bond TSV test using ring oscillators and multiple voltage levels
Defects in TSVs due to fabrication steps decrease the yield and reliability of 3D stacked ICs, hence these defects need to be… 
Highly Cited
2011
Highly Cited
2011
Integration of TSVs, wafer thinning and backside passivation on full 300mm CMOS wafers for 3D applications
Among the many 3D technology options that are being explored today, the 3D-stacked IC approach has become a mature and… 
Highly Cited
2011
Highly Cited
2011
How to select adhesive materials for temporary bonding and de-bonding of 200mm and 300mm thin-wafer handling for 3D IC integration?
Handling and shipping thin wafers (≦200μm) through all the semiconductor fabrication and packaging assembly processes are very… 
2010
2010
High temperature resistant bonding solutions enabling thin wafer processing (Characterization of polyimide base temporary bonding adhesive for thinned wafer handling)
Recent advanced devices including packaging and substrates required smart solution for wafer thinning and handling techniques. In… 
2008
2008
Reliability tests for a three dimensional chip stacking structure with through silicon via connections and low cost
In order to achieve the shorter circuit design of multiple chips, three-dimensional (3D) packaging technologies with through… 
Review
2008
Review
2008
Integration of high aspect ratio tapered silicon via for through-silicon interconnection
This paper provides a detailed overview of silicon carrier based packaging for 3D system in packaging application. In this work… 
2007
2007
Three dimensional chip stacking using a wafer-to-wafer integration
A three-dimensional (3D) wafer-to-wafer integration technology has been developed using face-to-face dielectric wafer bonding… 
2006
2006
Embedded active device packaging technology for next-generation chip-in-substrate package, CiSP
As the demands for high-density, high-speed, high-performance, and multi-function in portable electronic products, packaging… 
Highly Cited
2006
Highly Cited
2006
Factors affecting copper filling process within high aspect ratio deep vias for 3D chip stacking
Through-silicon-via (TSV) copper electrodes can provide shortest-length and highest-density connections with reduced signal delay… 
2004
2004
Z-axis interconnects using fine pitch, nanoscale through-silicon vias: Process development
A through-silicon via (TSV) process provides a means of implementing complex, multichip systems entirely in silicon, with a… 
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