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Memory-mapped I/O
Known as:
PMIO
, Port IO
, MMIO
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Memory-mapped I/O (MMIO) and port-mapped I/O (PMIO) (which is also called isolated I/O) are two complementary methods of performing input/output (I/O…
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Related topics
Related topics
49 relations
3 GB barrier
32-bit
8-bit
Address bus
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Papers overview
Semantic Scholar uses AI to extract papers important to this topic.
2016
2016
Energy-Efficiency of Millimeter-Wave Full-Duplex Relaying Systems: Challenges and Solutions
Zhongxiang Wei
,
Xu Zhu
,
Sumei Sun
,
Yi Huang
,
Ahmed Al-Tahmeesschi
,
Yufei Jiang
IEEE Access
2016
Corpus ID: 25065974
Full-duplex (FD) relaying is a promising solution for fifth generation (5G) wireless communications due to its potential to…
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2012
2012
Memory-mapped I/O over dual port BRAM on FPGA
R. Melo
,
D. M. Caruso
,
S. E. Tropea
VIII Southern Conference on Programmable Logic
2012
Corpus ID: 40721346
Nowadays, Direct Memory Access (DMA) is one of the most used mechanisms for data transfer between a processor and its peripherals…
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2010
2010
IR indoor localization and wireless transmission for motion control in smart building applications based on Wiimote technology
Po-Wei Chen
,
K. Ou
,
Kuo-Shen Chen
Proceedings of SICE Annual Conference
2010
Corpus ID: 8479688
With the implementation of sensors and actuators into buildings, spaces therefore have sensing ability, flexibility, and…
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Highly Cited
2008
Highly Cited
2008
Network Coding for Two-Way Relay Channels using Lattices
Ihn-Jung Baik
,
Sae-Young Chung
IEEE International Conference on Communications
2008
Corpus ID: 29482403
In this paper, we propose a network coding using a lattice for the two-way relay channel with two nodes communicating…
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Highly Cited
2007
Highly Cited
2007
Efficient Handling of N-gram Language Models for Statistical Machine Translation
Marcello Federico
,
M. Cettolo
WMT@ACL
2007
Corpus ID: 603858
Statistical machine translation, as well as other areas of human language processing, have recently pushed toward the use of…
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Highly Cited
2002
Highly Cited
2002
Embedded timing analysis: a soc infrastructure
S. Tabatabaei
,
A. Ivanov
IEEE Design & Test of Computers
2002
Corpus ID: 23219114
This SoC infrastructure core is a flexible, scalable, and highly accurate embedded time interval analyzer (ETIA), used to measure…
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2000
2000
Smart-pixel array technology for free-space optical interconnects
Yue Liu
,
E. Strzelecka
,
J. Nohava
,
M. K. Hibb-Brenner
,
E. Towe
Proceedings of the IEEE
2000
Corpus ID: 39939991
This paper describes a smart-pixel array technology that is being developed at Honeywell for use in chip-to-chip optical…
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Highly Cited
1985
Highly Cited
1985
Assessment of errors involved in the determination of interproton distance ratios and distances by means of one- and two-dimensional NOE measurements
G. Clore
,
A. Gronenborn
1985
Corpus ID: 51746527
1981
1981
A versatile memory-mapped I/O interface for microcomputers
N. Osaka
1981
Corpus ID: 57471135
An inexpensive and easy-to-bulid input/output interface capable of driving the electromechanical loads (relays, solenoids, dc…
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Review
1981
Review
1981
The first decade of Gloria
A. Laughton
1981
Corpus ID: 128756145
In 10 years of operation, GLORIA has been used on 26 cruises and has inonified more than 1% of the ocean floor. The paper reviews…
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