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Intel Core (microarchitecture)

Known as: Intel Core microarchitecture, Intel Core 2 Solo ULV, Intel Core Architecture 
The Intel Core microarchitecture (previously known as the Next-Generation Micro-Architecture) is a multi-core processor microarchitecture unveiled by… 
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BIOSCPU cacheCPU power dissipationCPUID

Papers overview

Semantic Scholar uses AI to extract papers important to this topic.
2014
2014
CIVSched: A Communication-Aware Inter-VM Scheduling Technique for Decreased Network Latency between Co-Located VMs
Server consolidation in cloud computing environments makes it possible for multiple servers or desktops to run on a single… 
2013
2013
Design and analysis of schedules for virtual network migration
The Internet faces well-known challenges in realizing modifications to the core architecture. To help overcome these limitations… 
Highly Cited
2009
Highly Cited
2009
A family of 45nm IA processors
Nehalem is a family of next-generation IA processors for mobile, desktop and server segments implemented in 45nm high-κ metal… 
2009
2009
TAPE: Thermal-aware agent-based power econom multi/many-core architectures
A growing challenge in embedded system design is coping with increasing power densities resulting from packing more and more… 
2009
2009
Architectural support for cilk computations on many-core architectures
Future generations of high performance processors have the potential to integrate tens to hundreds of processing cores in a… 
2009
2009
Adaptive Multi-versioning for OpenMP Parallelization via Machine Learning
The introduction of multi-core architectures generates a higher demand for parallelism in order to fully exploit the potential of… 
Highly Cited
2006
Highly Cited
2006
NEDA: a low-power high-performance DCT architecture
Conventional distributed arithmetic (DA) is popular in application-specific integrated circuit (ASIC) design, and it features on… 
Highly Cited
2004
Highly Cited
2004
A 0.18 /spl mu/m 3.0 V 64 Mb non-volatile phase-transition random-access memory (PRAM)
A non-volatile 64 Mb phase-transition RAM is developed by fully integrating a chalcogenide alloy GST (Ge/sub 2/Sb/sub 2/Te/sub 5… 
2001
2001
Frame-level pipelined motion estimation array processor
A systolic motion estimation processor (MEP) core architecture implementing the full-search block-matching (FSBM) algorithm is… 
2000
2000
Power estimation approach for SRAM-based FPGAs
This paper presents the power consumption estimation for the novel Virtex architecture. Due to the fact that the XC4000 and the… 
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