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Half-precision floating-point format
Known as:
Float16
, Half-float
, Half-precision
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In computing, half precision is a binary floating-point computer number format that occupies 16 bits (two bytes in modern computers) in computer…
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Papers overview
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2018
2018
IMPLEMENTATION OF HALF PRECISION FLOATING POINT ARITHMETIC OPERATIONS FOR DSP APPLICATIONS
Miss. Supriya
,
Sunil Phalle
,
Prof. M.R.Jadhav
2018
Corpus ID: 69534784
—For dealing with digital signals in real time, parameters like, speed of operation, hardware requirement, power and area, must…
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2018
2018
Impact of Vectorization Over 16-bit Data-Types on GPUs
Luís Reis
,
Ricardo Nobre
,
João MP Cardoso
PARMA-DITAM '18
2018
Corpus ID: 3980336
Since the introduction of Single Instruction Multiple Thread (SIMT) GPU architectures, vectorization has seldom been recommended…
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2018
2018
Half-precision Floating Point on Spiking Neural Networks Simulations in FPGA
C. Zambelli
,
J. Ranhel
IEEE International Joint Conference on Neural…
2018
Corpus ID: 52988708
The use of half-precision floating-point numbers (hFP) in simulations of spiking neural networks (SNN) was investigated. The hFP…
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2017
2017
Towards numerical benchmark for half-precision floating point arithmetic
P. Luszczek
,
J. Kurzak
,
I. Yamazaki
,
J. Dongarra
IEEE Conference on High Performance Extreme…
2017
Corpus ID: 37287001
With NVIDA Tegra Jetson X1 and Pascal P100 GPUs, NVIDIA introduced hardware-based computation on FP16 numbers also called half…
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2011
2011
Fully Gravure Printed Half Adder on Plastic Foils
J. Noh
,
Sungho Kim
,
Kyunghwan Jung
,
Joonseok Kim
,
Sungho Cho
,
Gyoujin Cho
IEEE Electron Device Letters
2011
Corpus ID: 34198292
All-printed half adders will be the first step to the way of printing an arithmetic logic unit which will be further expanded to…
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2010
2010
A decimal floating-point fused-multiply-add unit
R. Samy
,
H. Fahmy
,
R. Raafat
,
A. Mohamed
,
Tarek ElDeeb
,
Yasmin Farouk
53rd IEEE International Midwest Symposium on…
2010
Corpus ID: 2145225
This paper presents the first hardware implementation of a fully parallel decimal floating-point fused-multiply-add unit…
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2009
2009
Design and Implementation and On-Chip High-Speed Test of SFQ Half-Precision Floating-Point Adders
Heejoung Park
,
Y. Yamanashi
,
+8 authors
Shuichi Nagasawa
IEEE transactions on applied superconductivity
2009
Corpus ID: 9640373
We are developing a large-scale reconfigurable data-path (LSRDP) based on single-flux-quantum (SFQ) circuits to establish a…
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2008
2008
A broad spectrum neutron spectrometer utilizing a high energy Bonner sphere extension
E. Burgett
2008
Corpus ID: 125658390
2005
2005
A low-leakage twin-precision multiplier using reconfigurable power gating
Magnus Själander
,
Mindaugas Drazdziulis
,
P. Larsson-Edefors
,
H. Eriksson
IEEE International Symposium on Circuits and…
2005
Corpus ID: 1850733
A twin-precision multiplier that uses reconfigurable power gating is presented. Employing power cut-off techniques in…
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2004
2004
The accuracy of dual energy X-ray absorptiometry (DXA), weight, and P2 back fat to predict half-carcass and primal-cut composition in pigs within and across research experiments
D. Suster
,
B. Leury
,
C. Hofmeyr
,
D. D'Souza
,
F. Dunshea
2004
Corpus ID: 5183561
A Hologic QDR4500A dual energy X-ray absorptiometer (DXA) was used to measure body composition in 199 half-carcasses ranging from…
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