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DPLL algorithm

Known as: Davis-Putnam-Logemann-Loveland algorithm, Davis–Putnam–Logemann–Loveland algorithm, DPLL-Algorithm 
In computer science, the Davis–Putnam–Logemann–Loveland (DPLL) algorithm is a complete, backtracking-based search algorithm for deciding the… 
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Related topics

Related topics

34 relations
Answer set programmingAutomated planning and schedulingAutomated theorem provingBackjumping

Broader (1)

Constraint programming

Papers overview

Semantic Scholar uses AI to extract papers important to this topic.
2016
2016
An 802.11 a/b/g/n digital fractional-N PLL with automatic TDC linearity calibration for spur cancellation
This work presents a 1.9~5.6 GHz fractional-N DPLL with digi-phase spur canceller. It utilizes a ramp signal generated from the… 
2014
2014
Abstract satisfaction
This article introduces an abstract interpretation framework that codifies the operations in SAT and SMT solvers in terms of… 
Highly Cited
2012
Highly Cited
2012
A 0.004mm2 250μW ΔΣ TDC with time-difference accumulator and a 0.012mm2 2.5mW bang-bang digital PLL using PRNG for low-power SoC applications
As digital CMOS technology scales to 32nm and below, small and low-voltage clock and timing generators are in high demand to… 
2010
2010
A calibration-free 800MHz fractional-N digital PLL with embedded TDC
Digital Phase-Locked Loops (DPLLs), which are amenable to CMOS process scaling, have recently been demonstrated for both wireless… 
2008
2008
Data Compression for Proof Replay
We describe a compressing translation from SAT solver generated propositional resolution refutation proofs to classical natural… 
2007
2007
Technique to Reduce the Resolution Requirement of Digitally Controlled Oscillators for Digital PLLs
Phase-locked loops (PLLs) are a critical component in modern systems. Digital PLLs (DPLLs) are increasingly popular in CMOS… 
2006
2006
Design of a 1GHz Digital PLL Using 0.18\mu m CMOS Technology
A digital phase-locked loop (DPLL) is designed and is shown to have 1GHz operation with lock time of 643.36ns. The lock time was… 
1996
1996
Frequency granularity in digital phaselock loops
The frequency of a digital phaselock loop (DPLL) is necessarily quantized. Feedback around the quantizing nonlinearity leads to a… 
Highly Cited
1989
Highly Cited
1989
All digital phase-locked loop: concepts, design and applications
The concepts of an all digital phase-locked loop (DPLL), which contains a purely digital phase detector, loop filter and voltage… 
Highly Cited
1989
Highly Cited
1989
Secure random number generation using chaotic circuits
The authors show how to use a chaotic circuit as a secure random number generator and given an example using a first-order… 
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