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Carry-select adder

Known as: Carry select adder, Conditional sum adder 
In electronics, a carry-select adder is a particular way to implement an adder, which is a logic element that computes the -bit sum of two -bit… 
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Related topics

Related topics

6 relations
Adder (electronics)Carry-lookahead adderFan-outKogge–Stone adder

Papers overview

Semantic Scholar uses AI to extract papers important to this topic.
2011
2011
A very fast and low power carry select adder circuit
Carry Select Adder (CSA) is known to be the fastest adder among the conventional adder structures. It is used in many data… 
2011
2011
Design of Area and Power Efficient Modified Carry Select Adder
Adders are one of the widely used digital components in digital integrated circuit design. The Carry Select Adder (CSA) provides… 
2008
2008
High-Performance Carry Select Adder Using Fast All-One Finding Logic
A carry-select adder(CSA) can be implemented by using single ripple carry adder and an add-one circuit instead of using dual… 
2005
2005
A technique for modular design of self-checking carry-select adder
The carry-select adders provide significant speed improvement over other types of adders. This paper proposes a new approach for… 
2004
2004
A hybrid Ling carry-select adder
  • J. GradJ. Stine
  • Conference Record of the Thirty-Eighth Asilomar…
  • 2004
  • Corpus ID: 24198146
Hybrid adders, combining a sparse carry-lookahead tree and a carry-select output stage are a well-known implementation form of… 
2004
2004
A gate-level strategy to design Carry Select Adders
This paper addresses the gate-level design of Carry Select Adders aiming at minimizing its delay through a proper selection of… 
2003
2003
A modulo p checked self-checking carry select adder
In this paper a new self-checking carry select adder is proposed. The duplicated adder blocks which are inherent to a carry… 
2003
2003
On-line detection of faults in carry-select adders
  • B. K. KumarP. Lala
  • International Test Conference, . Proceedings. ITC…
  • 2003
  • Corpus ID: 17044984
Paper 35.3 91 2 from the previous stage. If the actual carry-in is ‘0’ then the sum multiplexed from the first unit is selected… 
2002
2002
A carry-select-adder optimization technique for high-performance Booth-encoded Wallace-tree multipliers
We present a carry-select-adder partitioning algorithm for high-performance Booth-encoded Wallace-tree multipliers. By taking… 
2001
2001
High-performance low-power carry select adder using dual transition skewed logic
In this paper, we present a low power and high performance Carry Select Adder (CSA) using Dual Transition Skewed Logic (DTSL… 
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