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Carry-save adder
Known as:
CSA
, Carry save adder
A carry-save adder is a type of digital adder, used in computer microarchitecture to compute the sum of three or more n-bit numbers in binary. It…
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Related topics
Related topics
11 relations
Adder (electronics)
Adder–subtractor
Carry (arithmetic)
Carry-lookahead adder
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Papers overview
Semantic Scholar uses AI to extract papers important to this topic.
2018
2018
Fault Tolerant Carry Save Adders - A NMR Configuration Approach
S. Radhakrishnan
,
T. Nirmalraj
,
S. Ashwin
,
V. Elamaran
,
R. K. Karn
International Conference on Control, Power…
2018
Corpus ID: 56175785
In digital systems design, the high-speed adders play an imperative role in modules like adders, multipliers, division, etc. to…
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2016
2016
LOW POWER AND HIGH SPEED CARRY SAVE ADDER USING MODIFIED GATE DIFFUSION INPUT TECHNIQUE
P. Kishore
,
K. Babulu
,
P. Sridevi
2016
Corpus ID: 189955024
Low power and high speed adders are the most essential components of every contemporary signal processing applications. Among the…
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2015
2015
Modified energy efficient carry save adder
Benisha Bennet
,
S. Maflin
International Conference on Circuits, Power and…
2015
Corpus ID: 17583224
The main aim of the paper is to produce the asynchronous energy efficient of the carry save adder. In the past decade, the VLSI…
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Highly Cited
2008
Highly Cited
2008
A new high dynamic range moduli set with efficient reverse converter
A. Hariri
,
K. Navi
,
R. Rastegar
Computers and Mathematics with Applications
2008
Corpus ID: 34211447
2004
2004
A low latency and low power dynamic Carry Save Adder
R. Datta
,
J. Abraham
,
+5 authors
K. Nowka
IEEE International Symposium on Circuits and…
2004
Corpus ID: 6643258
This paper presents a 4-to-2 Carry Save Adder (CSA) using dynamic logic and the Limited Switch Dynamic Logic (LSDL) circuit…
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2002
2002
A staged carry-save-adder array for Montgomery modular multiplication
Jhing-Fa Wang
,
Po-Chuan Lin
,
P. Chiu
Proceedings. IEEE Asia-Pacific Conference on ASIC…
2002
Corpus ID: 62168580
In this paper, an efficient VLSI architecture to compute the n-bit Montgomery modular multiplication is proposed. By using the…
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2001
2001
Minimum-adder integer multipliers using carry-save adders
O. Gustafsson
,
H. Ohlsson
,
L. Wanhammar
ISCAS . The IEEE International Symposium on…
2001
Corpus ID: 8877034
In this paper we investigate graph-based minimum-adder integer multipliers using carry-save adders. The previously proposed…
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1999
1999
Bit-level arithmetic optimization for carry-save additions
Kei-Yong Khoo
,
Zhan Yu
,
A. Willson
IEEE/ACM International Conference on Computer…
1999
Corpus ID: 12668400
Addresses the bit-level optimization of carry-save adder (CSA) arrays when the operands are of unequal wordlength (such as in…
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1996
1996
Transition reduction in carry-save adder trees
P. Larsson
,
C. Nicol
Proceedings / International Symposium on Low…
1996
Corpus ID: 14380655
By taking advantage of the redundancy in a 4-2 compressor, we reduce the number of transitions in carry-save adder trees that are…
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1974
1974
Fault-Tolerant Carry-Save Adders
D. Pradhan
IEEE transactions on computers
1974
Corpus ID: 38987307
In this correspondence a design of fault-tolerant carry-save adders is presented. The design of fault-tolerant carry-save adders…
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