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Bit-level parallelism
Known as:
Bitlevel parallelisms
, Bit-level devices
, Bit levels
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Bit-level parallelism is a form of parallel computing based on increasing processor word size. From the advent of very-large-scale integration (VLSI…
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Related topics
Related topics
14 relations
16-bit
32-bit
4-bit
8-bit
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Broader (1)
Parallel computing
Papers overview
Semantic Scholar uses AI to extract papers important to this topic.
2018
2018
Detecting rogue attacks on commercial wireless Insteon home automation systems
Christopher M. Talbot
,
Michael A. Temple
,
T. Carbino
,
J. Betances
Computers & security
2018
Corpus ID: 9782449
2011
2011
A Novel Chaos-based Image Encryption Scheme with an Improved Permutation Process
Xin Ma
,
Chong Fu
,
W. Lei
,
Shuo Li
2011
Corpus ID: 14047660
Confidentiality is an important issue when digital images are transmitted over public networks, and encryption is the most useful…
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Highly Cited
2011
Highly Cited
2011
A frequent-value based PRAM memory architecture
Guangyu Sun
,
Dimin Niu
,
Ouyang Jin
,
Yuan Xie
Asia and South Pacific Design Automation…
2011
Corpus ID: 16072514
Phase Change Random Access Memory (PRAM) has great potential as the replacement of DRAM as main memory, due to its advantages of…
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Highly Cited
2009
Highly Cited
2009
Focal-Plane Algorithmically-Multiplying CMOS Computational Image Sensor
Alireza Nilchi
,
J. Aziz
,
R. Genov
IEEE Journal of Solid-State Circuits
2009
Corpus ID: 17015364
The CMOS image sensor computes two-dimensional convolution of video frames with a programmable digital kernel of up to 8 times 8…
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Highly Cited
2007
Highly Cited
2007
Reconfigurable Computing Systems (Rekonfigurierbare Rechensysteme)
J. Teich
it - Information Technology
2007
Corpus ID: 17719672
Ongoing technological innovation and success in the miniaturization and fabrication of sub-micron microelectronic devices have…
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Highly Cited
2005
Highly Cited
2005
Platform-based design from parallel C specifications
I. Augé
,
F. Pétrot
,
François Donnet
,
P. Gomez
IEEE Transactions on Computer-Aided Design of…
2005
Corpus ID: 18616300
This paper presents Disydent, a framework dedicated to system-on-a-chip (SoC) platform-based design for shared memory multiple…
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Highly Cited
2002
Highly Cited
2002
Bluetooth and IEEE 802.11 coexistence: analytical performance evaluation in fading channel
A. Conti
,
D. Dardari
,
G. Pasolini
,
O. Andrisano
IEEE International Symposium on Personal, Indoor…
2002
Corpus ID: 7751042
The performance in terms of the mean packet error probability (PEP) in a Rayleigh fading channel with thermal noise is…
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Highly Cited
2000
Highly Cited
2000
A simple processor core design for DCT/IDCT
Tian-Sheuan Chang
,
Chin-Sheng Kung
,
C. Jen
IEEE Trans. Circuits Syst. Video Technol.
2000
Corpus ID: 12561673
This paper presents a cost-effective processor core design that features the simplest hardware and is suitable for discrete…
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Highly Cited
2000
Highly Cited
2000
A multiple input-multiple output channel model for simulation of Tx- and Rx-diversity wireless systems
M. Stege
,
J. Jelitto
,
M. Bronzel
,
G. Fettweis
,
Mannesmann Mobilfunk
Vehicular Technology Conference Fall . IEEE VTS…
2000
Corpus ID: 17971886
Space-time receivers for wireless communication systems offer the possibility to have both Tx- and Rx-antennas. For a realistic…
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1996
1996
VLSI Implementation of a Selective Median Filter
Chun-Te Chen Chun-Te Chen
,
Liang-Gee Chen Liang-Gee Chen
. Digest of Technical Papers., International…
1996
Corpus ID: 31914935
0001 0 0 1 0 0011 0111 1001 In this paper, the VLSI implementation of a selective median filter for the real-time applications is…
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